Chen, Simin Ahn, Dae-Hwan An, Seong Ui Noh, Tae Hyeon Kim, Younghyun 2024-05-30T09:30:19Z 2024-05-30T09:30:19Z 2024-05-30 2024-07 0374-4884 https://pubs.kist.re.kr/handle/201004/149961 In this study, we propose a ferroelectric FET (FeFET) structure termed dual ferroelectric recessed channel FeFET (DF-RFeFET), employing metal-ferroelectric (FE)-metal-FE-metal-SiO2 interlayer (IL)-silicon (MFMFMIS) structures. The DF-RFeFET is aimed at enhancing the memory window (MW) for high-performance memory applications. TCAD simulations with calibrated FE parameters and device models reveal that the DF-RFeFET can achieve a larger MW thanks to the enhanced geometric advantage to offer a strong and localized electric field at the inner ferroelectrics near the gate metal's corner. Moreover, design guidelines for the DF-RFeFET are suggested, including adjusting the inner and outer ferroelectric layers' thickness ratio and the recessed channel depth. The effects of introducing a relatively low-k oxide intermediate layer between dual ferroelectric layers and high-k gate stacks of IL on the MW have also been investigated. Through structural optimization, the DF-RFeFET demonstrated a record MW value of 5.5 V among the previously reported Si FeFETs. English 한국물리학회 TCAD simulation study of dual ferroelectric gate field-effect transistors with a recessed channel geometry for non-volatile memory applications Article 10.1007/s40042-024-01079-7 1 Journal of the Korean Physical Society, v.85, no.1, pp.47 - 55 Journal of the Korean Physical Society 85 1 47 55 N scie scopus kci ART003101304 001226566300001 2-s2.0-85193530581 Physics, Multidisciplinary Physics Article NM Ferroelectric FETs (FeFETs) Recessed channel MFMIS