Woo, Dong Yeon Noh, Gichang Park, Eunpyo Kim, Min Jee Lee, Dae Kyu Sung, Yong Woo Kim, Jaewook Jeong, YeonJoo Park, Jongkil Park, Seongsik Jang, Hyun Jae Choi, Nakwon Jo, Yooyeon Kwak, Joon Young 2024-11-15T12:30:20Z 2024-11-15T12:30:20Z 2024-11-12 2024-09 2634-4386 https://pubs.kist.re.kr/handle/201004/151074 In-memory computing facilitates efficient parallel computing based on the programmable memristor crossbar array. Proficient hardware image processing can be implemented by utilizing the analog vector-matrix operation with multiple memory states of the nonvolatile memristor in the crossbar array. Among various materials, 2D materials are great candidates for a switching layer of nonvolatile memristors, demonstrating low-power operation and electrical tunability through their remarkable physical and electrical properties. However, the intrinsic device-to-device (D2D) variation of memristors within the crossbar array can degrade the accuracy and performance of in-memory computing. Here, we demonstrate hardware image processing using the fabricated 2D hexagonal boron nitride-based memristor to investigate the effects of D2D variation on the hardware convolution process. The image quality is evaluated by peak-signal-to-noise ratio, structural similarity index measure, and Pratt’s figure of merit and analyzed according to D2D variations. Then, we propose a novel two-step gradual reset programming scheme to enhance the conductance uniformity of multiple states of devices. This approach can enhance the D2D variation and demonstrate the improved quality of the image processing result. We believe that this result suggests the precise tuning method to realize high-performance in-memory computing. English IOP Publishing Implementation of two-step gradual reset scheme for enhancing state uniformity of 2D hBN-based memristors for image processing Article 10.1088/2634-4386/ad3a94 1 Neuromorphic Computing and Engineering, v.4, no.3 Neuromorphic Computing and Engineering 4 3 Y scopus 2-s2.0-85198054559