Oh, Sun-Ho Kim, Jongchae Jang, Jaehyung Lee, Hanseung Yi, Suhyun Cho, Hoonmoo Kim, Namil Kwag, Pyongsu Gim, Yongtae Kim, Jongeun Byun, Kyungsu Kim, Minkyu Lee, Sangyoung Yoon, Seunghyun Cho, Ahyoung Baek, Taejun Park, Sooyoung Cho, Kwangjun Park, Eunsung Lee, Myung-jae Kim, Kyung-do Park, Wonje Cho, Juhyun Jeong, Hoesam Oh, Hoon-Sang Song, Changrock 2025-04-23T05:00:11Z 2025-04-23T05:00:11Z 2025-03-20 2024-09 1930-8833 https://pubs.kist.re.kr/handle/201004/152284 We fabricated a SPAD (Single Photon Avalanche Diode) array using 40 nm CMOS technology with 3D stacked backside-illuminated (BI) process. The optimization of the junction profile was conducted for two distinct SPAD pixel designs, incorporating N+/P well junctions to minimize dark noise while maximizing photon detection efficiency. Additionally, the influence of the guard ring on device performance was assessed. With the junction design with guard ring, we found it difficult to increase PDE (Photon Detection Efficiency) due to the strong trade-off between PDE and DCR (Dark Count Rate) while with the conventional junction design without guard, we could achieve the significantly a notable high PDE of 37% at 940 nm wavelength through the junction profile optimization work. In this work, we conclude that the simple junction design without guard structure is desirable for small pixel pitch SPAD devices in terms of achieving highly competitive SPAD device performance. English IEEE Junction design for high performance backside-illuminated single photo avalanche diodes Conference 10.1109/ESSERC62670.2024.10719528 1 50th IEEE European Solid-State Electronics Research Conference (ESSERC), pp.325 - 328 50th IEEE European Solid-State Electronics Research Conference (ESSERC) 325 328 US Bruges, BELGIUM 2024-09-09 2024 50TH IEEE EUROPEAN SOLID-STATE ELECTRONICS RESEARCH CONFERENCE, ESSERC 2024 001349548800082 2-s2.0-85208421923