Kim, Joon Pyo Kim, Seong Kwang Park, Seohak Kuk, Song-hyeon Kim, Tae yoon Kim, Bong Ho Ahn, Seong-Hun Cho, Yong-Hoon Jeong, YeonJoo Choi, Sung-Yool Kim, Sanghyeon 2024-01-12T02:33:26Z 2024-01-12T02:33:26Z 2023-01-30 2023-01 1530-6984 https://pubs.kist.re.kr/handle/201004/75854 The coming of the big-data era brought a need for power-efficient computing that cannot be realized in the Von Neumann architecture. Neuromorphic computing which is motivated by the human brain can greatly reduce power consumption through matrix multiplication, and a device that mimics a human synapse plays an important role. However, many synaptic devices suffer from limited linearity and symmetry without using incremental step pulse programming (ISPP). In this work, we demonstrated a charge-trap flash (CTF)-based synaptic transistor using trap-level engineered Al2O3/Ta2O5/Al2O3 gate stack for successful neuromorphic computing. This novel gate stack provided precise control of the conductance with more than 6 bits. We chose the appropriate bias for highly linear and symmetric modulation of conductance and realized it with very short (25 ns) identical pulses at low voltage, resulting in low power consumption and high reliability. Finally, we achieved high learning accuracy in the training of 60000 MNIST images. English American Chemical Society Dielectric-Engineered High-Speed, Low-Power, Highly Reliable Charge Trap Flash-Based Synaptic Device for Neuromorphic Computing beyond Inference Article 10.1021/acs.nanolett.2c03453 1 Nano Letters, v.23, no.2, pp.451 - 461 Nano Letters 23 2 451 461 N scie scopus 000920308600001 Chemistry, Multidisciplinary Chemistry, Physical Nanoscience & Nanotechnology Materials Science, Multidisciplinary Physics, Applied Physics, Condensed Matter Chemistry Science & Technology - Other Topics Materials Science Physics Article MEMORY ARRAYS REQUIREMENTS TRANSISTOR SYNAPSES NETWORK neuromorphic computing synaptic device charge trap flash gate stack nonlinearity