Eun sung Park Ha, Won-Yong Eom, Do Yoon Ahn, Daehwan An, Hyuk Yi, Suhyun Kim, Kyung-Do Kim, Jongchae Choi, Woo-Young Lee, Myung-Jae 2024-01-12T02:45:49Z 2024-01-12T02:45:49Z 2023-10-23 2023-06-15 https://pubs.kist.re.kr/handle/201004/76419 https://ieeexplore.ieee.org/document/10185229 We report on back-illuminated single-photon avalanche diodes (SPADs) based on 40 nm CIS technology. The SPAD performance is optimized with doping engineering, enabling the extension of the effective active area resulting in much higher efficiency. It achieves a dark count rate (DCR) of 15 cps/ μ m2, timing jitter of 97 ps, and excellent photon detection probability (PDP) in near-infrared (NIR) wavelength of about 60% at 905 nm and 44% at 940 nm at the excess bias voltage (VE) of 2.5 V. English Institute of Electrical and Electronics Engineers Inc. Doping-Optimized Back-illuminated Single-Photon Avalanche Diode in Stacked 40 nm CIS Technology Achieving 60% PDP at 905 nm Conference 10.23919/VLSITechnologyandCir57934.2023.10185229 1 2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023 2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023 JA Kyoto, Japan 2023-06-11 Digest of Technical Papers - Symposium on VLSI Technology