Chen, Simin Ahn, Dae-Hwan An, Seong Ui Kim, Younghyun 2024-01-12T02:47:35Z 2024-01-12T02:47:35Z 2023-09-08 2023 https://pubs.kist.re.kr/handle/201004/76505 Over the years, there has been much research on ferroelectric field-effect transistors (FeFETs) for memory applications. In this work, we propose a novel recessed channel FeFET with gate metalferroelectric (FE)-metal-FE-metal-SiO2 interlayer (IL)-silicon (MFMFMIS) gate stack, which is named a dual ferroelectric recessed channel FeFET (DFRFeFET) aimed to increase the memory window (MW) for high-performance memory applications. With calibrated FE parameters and device models in technology computer-aided design (TCAD) simulation, we found that the DF-RFeFET can have a large MW of 3.2 V. In addition, guidelines for the DF-RFeFET design are provided in terms of the thickness ratio of the inner and outer FE layers to maximize the MW. English IEEE Simulation of a Recessed Channel Ferroelectric-Gate Field-Effect Transistor with a Dual Ferroelectric Gate Stack for Memory Application Conference 10.1109/EDTM55494.2023.10103116 1 7th IEEE Electron Devices Technology and Manufacturing Conference (EDTM) 7th IEEE Electron Devices Technology and Manufacturing Conference (EDTM) US Seoul, SOUTH KOREA 2023-03-07 2023 7TH IEEE ELECTRON DEVICES TECHNOLOGY & MANUFACTURING CONFERENCE, EDTM 001004185500184 2-s2.0-85158162774