Dae-Young Jeon So Jeong Park Mireille Mouis Sylvain Barraud Gyu-Tae Kim Gerard Ghibaudo 2024-01-12T05:40:51Z 2024-01-12T05:40:51Z 2021-09-29 2019-04 2330-5738 https://pubs.kist.re.kr/handle/201004/78966 Unique electrical properties of junctionless transistors (JLTs) with back-gate bias (Vgb) effects are investigated and visualized by numerical simulations. Charge coupling effects between front and back interfaces influenced threshold voltage (Vth) and flat-band voltage (Vfb) of JLTs. In addition, series resistance (Rsd) of JLTs was dependent on Vgb and back-biasing behavior of JLT with a shorter channel was deviated from intrinsic characteristics due to considerable Rsd effects. The Rsd was extracted by transfer length method (TLM) and its effects were deembedded using simple equation. English IEEE Series resistance null Back-gate effects null Junctionless transistors null Threshold voltage null Flat-band voltage Series Resistance Effects on the Back-gate Biased Operation of Junctionless Transistors Conference 1 EUROSOI-ULIS2019 EUROSOI-ULIS2019 FR Grenoble, France 2019-04-01 2019 JOINT INTERNATIONAL EUROSOI WORKSHOP AND INTERNATIONAL CONFERENCE ON ULTIMATE INTEGRATION ON SILICON (EUROSOI-ULIS) 000565067300067 2-s2.0-85083160657