Jin soo Park Kim Jung Yeon Ji-Hoon Lee Hee-Kyoung Bae Jinsik Kim Kyo Seon Hwang Jung Ho Park Rino Choi Lee, Byung Chul 2024-01-12T06:13:13Z 2024-01-12T06:13:13Z 2021-09-29 2017-09 1948-5719 https://pubs.kist.re.kr/handle/201004/79484 In this paper, we present a full analytical model that can simulate an entire CMUT-FET structure with high accuracy and fast computation. Using the proposed analytical model, electromechanical properties, electrical characteristics (Id-Vg), and pressure sensitivity of the CMUT-FET are simulated and analyzed. The optimal bias point of the CMUT-FET is found to be1.3 V (Sub-threshold operation), at which the calculated pressure sensitivity is 2.584 × 10-6 Pa-1. This optimum bias point is almost 11 times lower than 80 % pull-in voltage for conventional highfrequency CMUTs. As a consecutive work, we also report on a fabrication process of the CMUT-FET with nickel-silicided source/drain junctions and low-temperature wafer bonding. The low-temperature wafer bonding successfully demonstrates the direct integration of CMUT on FET, which is verified via cross sectional inspection. The fabrication technique is a promising solution and can be developed further to for integration with ICs. English IEEE Field-effect transistor-embedded capacitive micromachined ultrasonic transducer(CMUT-FET) high-frequency operation analytical model low-temperature wafer bonding Analytical Calculation and Fabrication of FET-Embedded Capacitive Micromachined Ultrasonic Transducer Conference 1 IEEE International Ultrasonics Symposium 2017, pp.1 - 4 IEEE International Ultrasonics Symposium 2017 1 4 US 미국 2017-09-06 2017 IEEE INTERNATIONAL ULTRASONICS SYMPOSIUM (IUS) 000416948401014 2-s2.0-85039459300