Cristoloveanu, S. Bawedin, M. Navarro, C. Chang, S.-J. Wan, J. Andrieu, F. Le, Royer C. Rodriguez, N. Gamiz, F. Zaslavsky, A. Kim, Y.T. 2024-01-12T06:53:35Z 2024-01-12T06:53:35Z 2022-03-07 2015-05 1938-5862 https://pubs.kist.re.kr/handle/201004/80277 Several types of floating-body capacitorless 1T-DRAM memory cells with planar SOI or multi-gate configuration are reviewed and compared. We show that 1T-DRAMs are also compatible with the 'unified memory' paradigm which aims at combining, within a single SOI transistor, volatile, nonvolatile and multiple-state memory functionalities. We focus on our recently proposed concepts (MSDRAM, A2RAM and Z2-FET), by addressing the device architecture and fabrication, operating mechanisms, and scaling issues. Experimental results together with numerical simulations indicate the directions for performance optimization. ？ The Electrochemical Society. English Electrochemical Society Inc. Special memory mechanisms in SOI devices Conference 10.1149/06605.0201ecst 1 Symposium on Advanced CMOS-Compatible Semiconductor Devices 17 - 227th ECS Meeting, pp.201 - 210 Symposium on Advanced CMOS-Compatible Semiconductor Devices 17 - 227th ECS Meeting 201 210 US 2015-05-24 ECS Transactions 2-s2.0-84931326209