Park, Y.-K. Kim, Y.-K. Kim, H. Lee, D.-J. Kim, C.-J. Ju, B.-K. Park, J.-O. 2024-01-12T09:11:59Z 2024-01-12T09:11:59Z 2022-03-07 2003-01 0000-0000 https://pubs.kist.re.kr/handle/201004/83103 In this paper, as ultra thin silicon substrate was used as packaging substrate, we proposed ultra thin chip size RF-MEMS packaging technology that has vertical feed-through for low loss, as reduced the parasitic capacity. Thin silicon wafer with 50um thickness was fabricated to achieve short electric path, low loss and lightweight. And then via holes with the diameter of 60um were fabricated and was filled by the RIE and electroplating process. Also, the wafer level bumps were fabricated for simple, low cost, and fine patterning process. The measured S-parameter of packaged CPW(Co-planner waveguide) has the reflection loss of under -19 dB and the insertion loss of -0.54 -0.67 dB. English IEEE A novel thin chip scale packaging of the RF-MEMS devices using ultra thin silicon Conference 1 IEEE Sixteenth Annual International Conference on Micro Electro Mechanical Systems, pp.618 - 621 IEEE Sixteenth Annual International Conference on Micro Electro Mechanical Systems 618 621 US Kyoto 2003-01-19 Proceedings of the IEEE Micro Electro Mechanical Systems (MEMS) 2-s2.0-0038494016