Reduction of channel resistance in amorphous oxide thin-film transistors with buried layer - Chong, Eugene; Kim, Bosul; Lee, Sang Yeol (E-MRS 2011 FALL SYMPOSIUM I: ADVANCES IN TRANSPARENT ELECTRONICS, FROM MATERIALS TO DEVICES III, 2012)
A silicon-indium-zinc-oxide (SIZO) thin film transistor (TFT) with low channel-resistance (R-CH) indium-zinc-oxide (In2O3:ZnO = 9:1) buried layer annealed at low temperature of 200 degrees C exhibited high field-effect mobility (mu(FE)) over 55.8 cm(2)/V.s which is 5 times higher than that of the conventional TFTs due to small threshold voltage (V-th) change of 1.8 V under bias-temperature stress (BTS) condition for 420 minutes. The low-R-CH buried-layer allows more strong current-path formed in channel layer well within relatively high-R-CH channel-layer since it is less affected by the channel bulk and/or back interface trap with high carrier concentration.