Ultra-low power 1T-DRAM in FDSOI technology - El Dirani, H.; Lee, K. H.; Parihar, M. S.; Lacord, J.; Martinie, S.; Barbe, J-Ch.; Mescot, X.; Fonteneau, P.; Broquin, J. -E.; Ghibaudo, G.; Galy, Ph; Gamiz, F.; et al. (ELSEVIER, 2017)
A systematic study of a capacitorless 1T-DRAM fabricated in 28 nm FDSOI technology is presented. The operation mechanism is based on band modulation. The Z(2)-FET memory cell features a large current sense margin and small OFF-state current at 25 degrees C and 85 degrees C. Moreover, low power consumption during state '1' writing is achieved with similar to 0.5 V programming voltage. These specifications make the Z(2)-FET an outstanding candidate for low-power eDRAM applications. (C) 2017 Elsevier B.V. All rights reserved.
Keywords: CAPACITORLESS 1T-DRAM; GATE; Z(2)-FET; DEVICES