Effect of surface treatment for the improvement of performance and patterning clarity of inkjet-printed transistor and inverter

Abstract

Printable semiconductor material-based thin film transistor is attractive for large area and low cost devices and circuit, which can be utilized for flexible and disposable electronics. In this study, effects of the surface treatment of gate insulator (patterned self assembly monolayer) on the resolution of the inkjet-patterned source-drain electrodes and transistor performance are systematically investigated. Both for simple silicon substrate as well as plastic film with patterned, printed gate, surface of the gate insulator was modified; various self-assembled monolayers (SAM; such as methacryloxy propyl trimethoxy silane [MPS], hexamethyldisilane [HMDS], and octadecyltrichlorosilane [OTS]) are tested for a control of Ag-ink spreading and pattern formation of source-drain electrodes. At each substrate, jetting profiles were precisely modified for optimum smooth-line patterning and the condition for best resolution with commercial 50um-diameter nozzle (Samsung Electro-Mechanics) was set. Stable printing condition with 40um-width patterned line on top of OTS-modified gate insulator was established. In order to fabricate more precisely controlled source-drain channel length, contact transfer process (CTP) of SAM using the pre-patterned PDMS mold was combined with conventional inkjet process. Both for the amorphous inorganic and organic (TIPS-pentacene) solution processible semiconductors, top and bottom-contact thin film transistors were fabricated with various channel length, which are controlled by inkjet and CTP process. Carrier mobility (ranging between 0.05 – 0.37 cm2/Vs), on/off ratio, and voltage threshold of TIPS-pentacene based transistor was analyzed, while the fabrication process of inverter devices were optimized toward a better design of printed ring oscillator.