Proposal of P-Channel FE NAND with High Drain Current and Feasible Disturbance for Next Generation 3D NAND

Abstract

Recently the demand for higher drain current and scalable gate stack thickness arises for next-generation 3D NAND flash, due to the physical limit of cells and stacked layers over 1,000. While the N-channel ferroelectric field-effect-transistor (n-FEFET) has been studied to overcome the limit, it brings the critical reliability issue due to parasitic electron trapping during the program and read, which degrades retention, endurance and induces disturbance and cell failure. We show the feasibility of 2-bit multi-level-cell (MLC) p-channel FEFET (p-FEFET) for (embedded) NAND flash memory application. P-FEFET intrinsically has higher on-current than n-FEFET. It is due to the absence of hole trapping, which leads to ferroelectric charge boosting at the channel. Other properties (retention, disturbance, etc) also show that p-FEFET has remarkably improved electrical characteristics when it is targeted for NAND flash, rather than n-FEFET. Finally, we propose a strategy for engineering the p-FENAND device.