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dc.contributor.authorSung-Kyun Lee-
dc.contributor.authorKim Yong Tae-
dc.contributor.authorKim Seong Il-
dc.contributor.author이철의-
dc.date.accessioned2024-01-13T14:00:53Z-
dc.date.available2024-01-13T14:00:53Z-
dc.date.created2021-09-29-
dc.identifier.urihttps://pubs.kist.re.kr/handle/201004/107547-
dc.languageEnglish-
dc.subjectferroelectric gate-
dc.titleRelationships among coercive voltage, memory window and electric distribution in ferroelectric gate structure-
dc.typeConference-
dc.description.journalClass1-
dc.identifier.bibliographicCitationFerroelectric Materials Application, pp.209 - 210-
dc.citation.titleFerroelectric Materials Application-
dc.citation.startPage209-
dc.citation.endPage210-
dc.citation.conferencePlaceJA-
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KIST Conference Paper > Others
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