Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Kim, Gwang-Bok | - |
dc.contributor.author | Kim, Taikyu | - |
dc.contributor.author | Choi, Cheol Hee | - |
dc.contributor.author | Chung, Sang Won | - |
dc.contributor.author | Jeong, Jae Kyeong | - |
dc.date.accessioned | 2024-01-19T09:03:50Z | - |
dc.date.available | 2024-01-19T09:03:50Z | - |
dc.date.created | 2023-08-24 | - |
dc.date.issued | 2023-07 | - |
dc.identifier.issn | 0741-3106 | - |
dc.identifier.uri | https://pubs.kist.re.kr/handle/201004/113489 | - |
dc.description.abstract | This study shows the effect of single spinel phase crystallization on drain-induced barrier lowering (DIBL) of indium-zinc-tin-oxide (IZTO) thin-film transistors (TFTs) with submicron channel length. The 0.9-mu m-long amorphous IZTO (a-IZTO) TFT shows a poor DIBL of 318 mV/V. In contrast, a significant improvement in the DIBL is achieved in the single spinel phase IZTO (s-IZTO) TFT, which could be attributed to the suppression of lateral diffusion of oxygen vacancy (VO) and low VO defects through crystallization-induced enforcement of metal-oxygen bonds. Consequently, 0.9-mu m-long s-IZTO TFT reveals a small DIBL of 92 mV/V as well as a high field-effect mobility of 90.1 cm(2)/Vs and a low subthreshold swing of 0.1 V/dec. In addition, reliability against external bias temperature stress is considerably improved through single-phase crystallization, leading to an insignificant threshold voltage shift of +0.4 (-0.4) V under positive (negative) bias stress with electric field of 2 (-2) MV/cm at 60 degrees C for 10,000 s, respectively, in the 0.9-mu m-long s-IZTO TFT. | - |
dc.language | English | - |
dc.publisher | Institute of Electrical and Electronics Engineers | - |
dc.title | Effect of Single Spinel Phase Crystallization on Drain-Induced-Barrier-Lowering in Submicron Length IZTO Thin-Film Transistors | - |
dc.type | Article | - |
dc.identifier.doi | 10.1109/LED.2023.3274670 | - |
dc.description.journalClass | 1 | - |
dc.identifier.bibliographicCitation | IEEE Electron Device Letters, v.44, no.7, pp.1132 - 1135 | - |
dc.citation.title | IEEE Electron Device Letters | - |
dc.citation.volume | 44 | - |
dc.citation.number | 7 | - |
dc.citation.startPage | 1132 | - |
dc.citation.endPage | 1135 | - |
dc.description.isOpenAccess | N | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.identifier.wosid | 001021302800026 | - |
dc.identifier.scopusid | 2-s2.0-85159843232 | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.relation.journalResearchArea | Engineering | - |
dc.type.docType | Article | - |
dc.subject.keywordPlus | CHANNEL | - |
dc.subject.keywordAuthor | Oxide semiconductor | - |
dc.subject.keywordAuthor | crystallization | - |
dc.subject.keywordAuthor | drain induced barrier lowering | - |
dc.subject.keywordAuthor | thin-film transistor | - |
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