A Low-noise CMOS SPAD Pixel with 12.1 ps SPTR and 3 ns Dead Time

Abstract

In this paper, we present the first CMOS SPAD with performance comparable or better than that of the best custom SPADs, to date. The SPAD-based design, fully integrated in 180 nm CMOS technology, achieves a peak PDP of 55% at 480nm with a very broad spectrum spanning from NUV to NIF and a normalized DCR of 0.2cps/m2, both at 6V of excess bias. Thanks to a dedicated CMOS pixel circuit front-end, an afterpulsing probability of about 0.1% at a dead time of3ns were achieved. We designed three SPADs with a diameter of 25, 50, and 100m to study the impact of size on the timing jitter and to create a scaling law for SPADs. For these SPADs, a SPTR of 12.1ps, 16ps, and 27ps was achieved at 6V of excess bias, respectively. The SPADs operate in a wide range of temperatures, from -65C to 40C, reaching a normalized DCR of 1.6 mcps/m2 at 6V of excess bias. The proposed SPADs are ideal for a wide range of applications, including LiDAR, super-resolution microscopy, QRNGs, QKD, fluorescence lifetime imaging, time-resolved Raman spectroscopy, to name a few. CCBY