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dc.contributor.authorPark, Jongkil-
dc.contributor.authorJung, Sang-Don-
dc.date.accessioned2024-01-19T17:32:00Z-
dc.date.available2024-01-19T17:32:00Z-
dc.date.created2021-09-04-
dc.date.issued2020-06-
dc.identifier.issn1549-8328-
dc.identifier.urihttps://pubs.kist.re.kr/handle/201004/118589-
dc.description.abstractLearning plays an important role in the brain to make it adaptive to dynamical environments. This paper presents a presynaptic spike-driven spike timing-dependent plasticity (STDP) learning rule in the address domain for a neuromorphic architecture using a synaptic connectivity table in an external memory at a local routing node. We contribute two aspects to the implementation of the learning rule for extended large-scale neuromorphic systems. First, we reduced buffer sizes required for tracing a spike train which is required to pair all presynaptic and postsynaptic spike for an STDP time window. This method implements an exponential decay STDP function with two parameters: the latest timestamp and the synaptic modification rate at the latest timestamp. It reduces the required buffer size compared to previous works. Second, we resolve a lack of reverse lookup table issue with the presynaptic spike-driven algorithm. The proposed algorithm holds causal updates at postsynaptic spikes until a next presynaptic spike arrival. This approach removes the need of a reverse lookup table required at a postsynaptic spike. We show the implementation of the proposed algorithm in an FPGA device and validate it with a spiking neural network configuration. The experiment results show the proposed algorithm is comparable qualitatively with a conventional STDP learning rule.-
dc.languageEnglish-
dc.publisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC-
dc.subjectSYNAPTIC PLASTICITY-
dc.subjectMODEL-
dc.subjectNETWORK-
dc.subjectNEURONS-
dc.subjectSTDP-
dc.titlePresynaptic Spike-Driven Spike Timing-Dependent Plasticity With Address Event Representation for Large-Scale Neuromorphic Systems-
dc.typeArticle-
dc.identifier.doi10.1109/TCSI.2020.2966884-
dc.description.journalClass1-
dc.identifier.bibliographicCitationIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, v.67, no.6, pp.1936 - 1947-
dc.citation.titleIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS-
dc.citation.volume67-
dc.citation.number6-
dc.citation.startPage1936-
dc.citation.endPage1947-
dc.description.journalRegisteredClassscie-
dc.description.journalRegisteredClassscopus-
dc.identifier.wosid000543062600014-
dc.identifier.scopusid2-s2.0-85086011247-
dc.relation.journalWebOfScienceCategoryEngineering, Electrical & Electronic-
dc.relation.journalResearchAreaEngineering-
dc.type.docTypeArticle-
dc.subject.keywordPlusSYNAPTIC PLASTICITY-
dc.subject.keywordPlusMODEL-
dc.subject.keywordPlusNETWORK-
dc.subject.keywordPlusNEURONS-
dc.subject.keywordPlusSTDP-
dc.subject.keywordAuthorNeurons-
dc.subject.keywordAuthorNeuromorphics-
dc.subject.keywordAuthorHardware-
dc.subject.keywordAuthorField programmable gate arrays-
dc.subject.keywordAuthorRouting-
dc.subject.keywordAuthorHeuristic algorithms-
dc.subject.keywordAuthorRandom access memory-
dc.subject.keywordAuthorAddress domain-
dc.subject.keywordAuthorcolumn selectivity-
dc.subject.keywordAuthorreverse lookup table-
dc.subject.keywordAuthorSTDP-
dc.subject.keywordAuthorsynaptic table-
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