Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Park, Jongkil | - |
dc.contributor.author | Jung, Sang-Don | - |
dc.date.accessioned | 2024-01-19T17:32:00Z | - |
dc.date.available | 2024-01-19T17:32:00Z | - |
dc.date.created | 2021-09-04 | - |
dc.date.issued | 2020-06 | - |
dc.identifier.issn | 1549-8328 | - |
dc.identifier.uri | https://pubs.kist.re.kr/handle/201004/118589 | - |
dc.description.abstract | Learning plays an important role in the brain to make it adaptive to dynamical environments. This paper presents a presynaptic spike-driven spike timing-dependent plasticity (STDP) learning rule in the address domain for a neuromorphic architecture using a synaptic connectivity table in an external memory at a local routing node. We contribute two aspects to the implementation of the learning rule for extended large-scale neuromorphic systems. First, we reduced buffer sizes required for tracing a spike train which is required to pair all presynaptic and postsynaptic spike for an STDP time window. This method implements an exponential decay STDP function with two parameters: the latest timestamp and the synaptic modification rate at the latest timestamp. It reduces the required buffer size compared to previous works. Second, we resolve a lack of reverse lookup table issue with the presynaptic spike-driven algorithm. The proposed algorithm holds causal updates at postsynaptic spikes until a next presynaptic spike arrival. This approach removes the need of a reverse lookup table required at a postsynaptic spike. We show the implementation of the proposed algorithm in an FPGA device and validate it with a spiking neural network configuration. The experiment results show the proposed algorithm is comparable qualitatively with a conventional STDP learning rule. | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.subject | SYNAPTIC PLASTICITY | - |
dc.subject | MODEL | - |
dc.subject | NETWORK | - |
dc.subject | NEURONS | - |
dc.subject | STDP | - |
dc.title | Presynaptic Spike-Driven Spike Timing-Dependent Plasticity With Address Event Representation for Large-Scale Neuromorphic Systems | - |
dc.type | Article | - |
dc.identifier.doi | 10.1109/TCSI.2020.2966884 | - |
dc.description.journalClass | 1 | - |
dc.identifier.bibliographicCitation | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, v.67, no.6, pp.1936 - 1947 | - |
dc.citation.title | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS | - |
dc.citation.volume | 67 | - |
dc.citation.number | 6 | - |
dc.citation.startPage | 1936 | - |
dc.citation.endPage | 1947 | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.identifier.wosid | 000543062600014 | - |
dc.identifier.scopusid | 2-s2.0-85086011247 | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.relation.journalResearchArea | Engineering | - |
dc.type.docType | Article | - |
dc.subject.keywordPlus | SYNAPTIC PLASTICITY | - |
dc.subject.keywordPlus | MODEL | - |
dc.subject.keywordPlus | NETWORK | - |
dc.subject.keywordPlus | NEURONS | - |
dc.subject.keywordPlus | STDP | - |
dc.subject.keywordAuthor | Neurons | - |
dc.subject.keywordAuthor | Neuromorphics | - |
dc.subject.keywordAuthor | Hardware | - |
dc.subject.keywordAuthor | Field programmable gate arrays | - |
dc.subject.keywordAuthor | Routing | - |
dc.subject.keywordAuthor | Heuristic algorithms | - |
dc.subject.keywordAuthor | Random access memory | - |
dc.subject.keywordAuthor | Address domain | - |
dc.subject.keywordAuthor | column selectivity | - |
dc.subject.keywordAuthor | reverse lookup table | - |
dc.subject.keywordAuthor | STDP | - |
dc.subject.keywordAuthor | synaptic table | - |
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.