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dc.contributor.authorLee, Woo Chul-
dc.contributor.authorCho, Cheol Jin-
dc.contributor.authorPark, Suk-In-
dc.contributor.authorJun, Dong-Hwan-
dc.contributor.authorSong, Jin Dong-
dc.contributor.authorHwang, Cheol Seong-
dc.contributor.authorKim, Seong Keun-
dc.date.accessioned2024-01-19T22:03:46Z-
dc.date.available2024-01-19T22:03:46Z-
dc.date.created2021-09-03-
dc.date.issued2018-08-
dc.identifier.issn1567-1739-
dc.identifier.urihttps://pubs.kist.re.kr/handle/201004/121089-
dc.description.abstractThe presence of an AlN interfacial layer in high-k/In0.53Ga0.47As gate stacks improves the interfacial properties and enhances the electrical performance of devices. However, pure AlN is rarely grown by atomic layer deposition (ALD) because of the low reactivity of NH3 toward the common Al-precursor and the predisposition to oxidation of the grown AlN layer. Although a plasma-enhanced ALD technique significantly suppresses the oxygen content in the grown AlN layer, the deterioration of the interface properties by plasma-damage is a critical issue. In this work, an AlON interlayer was engineered by optimizing the NH3 feeding time in thermal ALD to improve the interface quality in Al2O3/AlON/In0.53Ga0.47As capacitors. It was determined that a mere increase in the NH3 feeding time during the ALD of the AlON film resulted in a higher nitrogen incorporation into the AlON interlayer, leading to a reduction in the interface trap density. Furthermore, the out-diffusion of elements from the In0.53Ga0.47As layer was effectively suppressed by increasing the NH3 feeding time. This work demonstrates that simple process optimization can improve the interface quality in high-k/In0.53Ga0.47As gate stacks without the use of any plasma-activated nitrogen source.-
dc.languageEnglish-
dc.publisherELSEVIER SCIENCE BV-
dc.subjectV COMPOUND SEMICONDUCTORS-
dc.subjectELECTRICAL-PROPERTIES-
dc.subjectPASSIVATION LAYER-
dc.subjectAL2O3-
dc.subjectDIELECTRICS-
dc.subjectDEVICES-
dc.subjectFILMS-
dc.titleEngineering of AlON interlayer in Al2O3/AlON/In0.53Ga0.47As gate stacks by thermal atomic layer deposition-
dc.typeArticle-
dc.identifier.doi10.1016/j.cap.2018.04.020-
dc.description.journalClass1-
dc.identifier.bibliographicCitationCURRENT APPLIED PHYSICS, v.18, no.8, pp.919 - 923-
dc.citation.titleCURRENT APPLIED PHYSICS-
dc.citation.volume18-
dc.citation.number8-
dc.citation.startPage919-
dc.citation.endPage923-
dc.description.journalRegisteredClassscie-
dc.description.journalRegisteredClassscopus-
dc.description.journalRegisteredClasskci-
dc.identifier.kciidART002375743-
dc.identifier.wosid000432852100010-
dc.identifier.scopusid2-s2.0-85046796494-
dc.relation.journalWebOfScienceCategoryMaterials Science, Multidisciplinary-
dc.relation.journalWebOfScienceCategoryPhysics, Applied-
dc.relation.journalResearchAreaMaterials Science-
dc.relation.journalResearchAreaPhysics-
dc.type.docTypeArticle-
dc.subject.keywordPlusV COMPOUND SEMICONDUCTORS-
dc.subject.keywordPlusELECTRICAL-PROPERTIES-
dc.subject.keywordPlusPASSIVATION LAYER-
dc.subject.keywordPlusAL2O3-
dc.subject.keywordPlusDIELECTRICS-
dc.subject.keywordPlusDEVICES-
dc.subject.keywordPlusFILMS-
dc.subject.keywordAuthorAlON-
dc.subject.keywordAuthorInGaAs-
dc.subject.keywordAuthorAtomic layer deposition-
dc.subject.keywordAuthorInterface trap density-
dc.subject.keywordAuthorMOS capacitor-
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KIST Article > 2018
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