Modified write-and-verify scheme for improving the endurance of multi-level cell phase-change memory using Ge-doped SbTe

Authors
Zhang, GangWu, ZheJeong, Jeung-hyunJeong, Doo SeokYoo, Won JongCheong, Byung-ki
Issue Date
2012-10
Publisher
PERGAMON-ELSEVIER SCIENCE LTD
Citation
SOLID-STATE ELECTRONICS, v.76, pp.67 - 70
Abstract
In this study, a modified write-and-verify (WAV) scheme is proposed for improving the programming/erasing (P/E) endurance of multi-level cell (MLC) phase-change memory (PCM) using Ge-doped SbTe (GeST). A dual reference data read method is developed to detect the level margin decay during P/E cycling, and a trigger condition is designed to trigger self-repair for the degraded cells before any P/E error for the modified WAV scheme. Experimental results suggest that the modified WAV scheme effectively extends the P/E endurance of PCM using GeST during 4-level P/E by at least 10 times. The modified WAV scheme is expected to improve the endurance of MLC-PCM of system applications. (C) 2012 Elsevier Ltd. All rights reserved.
Keywords
Modified WAV scheme; Endurance improvement; Phase-change memory
ISSN
0038-1101
URI
https://pubs.kist.re.kr/handle/201004/128844
DOI
10.1016/j.sse.2012.06.003
Appears in Collections:
KIST Article > 2012
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