Doping Engineering for PDP Optimization in SPADs Implemented in 55-nm BCD Process

Abstract

We introduce a new family of single-photon avalanche diodes (SPADs) with enhanced depletion regions in a 55-nm Bipolar-CMOS-DMOS (BCD) technology. We demonstrate how to systematically engineer doping profiles in the main junction and in deep p-well layers to achieve high sensitivity and low timing jitter. A family of sub 10 mu m SPADs was designed and fully characterized. With the increase of the well-defined depletion region, the breakdown voltages of three variants are 17.1, 20.6, and 23.0 V, respectively, the peak PDP wavelengths are 450 nm, 540 nm, and 640 nm, respectively. The timing jitter below 50 ps (FWHM) at 5 V excess bias voltage are achieved in SPAD1 and SPAD2. SPAD3 shows a high PDP over a wide spectral range, with a peak PDP of 41.3% at 640 nm, and 22.3% at 850 nm, and the timing jitter 96 ps at 3 V excess bias voltage. The proposed SPADs are suitable to low-pitch, large-format image sensors for high-speed, time-resolved applications and quantum imaging.