Full metadata record
DC Field | Value | Language |
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dc.contributor.author | Choi, Su-Hwan | - |
dc.contributor.author | Sim, Jae-Min | - |
dc.contributor.author | Shin, Jeongmin | - |
dc.contributor.author | Ryu, Seong-Hwan | - |
dc.contributor.author | Hwang, Taewon | - |
dc.contributor.author | Lim, So Young | - |
dc.contributor.author | Oh, Hye-Jin | - |
dc.contributor.author | Kwag, Jae-Hyeok | - |
dc.contributor.author | Lee, Jun-Yeoub | - |
dc.contributor.author | Song, Ki-Cheol | - |
dc.contributor.author | Lee, Yeonhee | - |
dc.contributor.author | Song, Minju | - |
dc.contributor.author | Kim, Junghwan | - |
dc.contributor.author | Park, Chang-Kyun | - |
dc.contributor.author | Song, Yun-Heub | - |
dc.contributor.author | Park, Jin-Seong | - |
dc.date.accessioned | 2025-01-20T02:00:44Z | - |
dc.date.available | 2025-01-20T02:00:44Z | - |
dc.date.created | 2025-01-17 | - |
dc.date.issued | 2024-12 | - |
dc.identifier.uri | https://pubs.kist.re.kr/handle/201004/151608 | - |
dc.description.abstract | Oxide semiconductors (OSs) are promising materials for NAND flash memory, offering the advantages of high field-effect mobility and superior large-area uniformity but suffering from low thermal stability, trade-off between mobility and stability, and the impossibility of the erase operation. To address these drawbacks, herein a hybrid-channel structure comprising heterostacked poly-Si and In-Ga-O (IGO) is developed. IGO is used as the main channel to achieve thermal stability above 800 degrees C, and the fabrication process is optimized to achieve superior electrical properties (mu FE = 103.66 cm2 V-1 s-1, subtreshold swing = 96 mV decade-1) and reliability (0.07 V positive shift during the positive bias temperature stress of 3 MV cm-1 at 100 degrees C for almost 3 h). Poly-Si is used to generate the gate-induced drain leakage current and enable the erase operation. The developed structure is used to fabricate 2D planar and three-layer stacked 3D NAND flash memories. The superior electrical properties (mu FE = 116.08 cm2 V-1 s-1, Ion = 4.73 mu A mu m-1) and deviations of the hybrid-channel NAND memory are comparable with those of its OS-channel counterpart. The use of the hybrid-channel structure in the NAND memories enables the realization of the erase operation with a large memory window (approximate to 3.60 V). | - |
dc.language | English | - |
dc.publisher | WILEY | - |
dc.title | Unveiling the Hybrid-Channel (poly-Si/IGO) Structure for 3D NAND Flash Memory for Improving the Cell Current and GIDL-Assisted Erase Operation | - |
dc.type | Article | - |
dc.identifier.doi | 10.1002/sstr.202400495 | - |
dc.description.journalClass | 1 | - |
dc.identifier.bibliographicCitation | Small Structures | - |
dc.citation.title | Small Structures | - |
dc.description.isOpenAccess | Y | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.identifier.scopusid | 2-s2.0-85212924345 | - |
dc.relation.journalWebOfScienceCategory | Chemistry, Physical | - |
dc.relation.journalWebOfScienceCategory | Nanoscience & Nanotechnology | - |
dc.relation.journalWebOfScienceCategory | Materials Science, Multidisciplinary | - |
dc.relation.journalResearchArea | Chemistry | - |
dc.relation.journalResearchArea | Science & Technology - Other Topics | - |
dc.relation.journalResearchArea | Materials Science | - |
dc.type.docType | Article; Early Access | - |
dc.subject.keywordPlus | ELECTRON | - |
dc.subject.keywordPlus | THIN-FILM TRANSISTORS | - |
dc.subject.keywordPlus | SI FILMS | - |
dc.subject.keywordPlus | OXIDE | - |
dc.subject.keywordPlus | MOBILITY | - |
dc.subject.keywordPlus | PERFORMANCE | - |
dc.subject.keywordPlus | THRESHOLD | - |
dc.subject.keywordAuthor | 3D NAND flash memories | - |
dc.subject.keywordAuthor | atomic layer deposition | - |
dc.subject.keywordAuthor | crystallinity | - |
dc.subject.keywordAuthor | gate-induced drain leakage erase operation | - |
dc.subject.keywordAuthor | hybrid channel (poly-Si/In-Ga-O) | - |
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