3D-Stacked Back-Illuminated Single-Photon Avalanche Diode Pixel With a Pitch of 3.5 μm

Abstract

Single-photon avalanche diode (SPAD) pixel scaling is essential to meet the increasing demands for high-resolution, compact, and power-efficient time-of-flight (ToF) sensing. In particular, the 3D-stacked approach enables aggressive pixel scaling by separating the SPAD and readout circuits into different wafers, thus maximizing the fill factor while minimizing the pixel pitch. However, pixel miniaturization often leads to degraded SPAD performance due to the premature edge breakdown (PEB) and the reduced number of photon-generated carriers that go through the avalanche multiplication region. In this work, we overcome these challenges by optimizing the doping profile to enhance the carrier collection in the device. We present a detailed analysis of the optimization progress by evaluating breakdown voltage (VB), dark count rate (DCR), and photon detection probability (PDP), highlighting the trade-offs and recovery achieved through successive doping refinements. The optimized device achieves a PDP of 37% and a timing jitter of 85 ps at 940 nm. Compared to prior 3D-stacked back-illuminated (BI) SPADs, our work exhibits one of the smallest pixel pitches to date, yet retains competitive PDP and jitter characteristics. This combination of aggressive scaling and robust performance positions the proposed SPAD as a promising solution for LiDAR, 3D imaging, and future wearable sensing systems.