DSpace at KISTKIST Patent2018

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dc.contributor.author고은정-
dc.contributor.author최정혜-
dc.date.accessioned2024-01-12T06:04:52Z-
dc.date.available2024-01-12T06:04:52Z-
dc.date.issued2020-11-05-
dc.identifier.urihttps://pubs.kist.re.kr/handle/201004/79322-
dc.title제일 원리에 기초한 MOS 소자의 얇은 게이트 산화막의 터널링 특성 분석 방법-
dc.typePatent-
dc.date.registration2020-11-05-
dc.date.application2018-12-11-
dc.identifier.patentRegistrationNumber10-2177751-
dc.identifier.patentApplicationNumber10-2018-0158977-
dc.publisher.countryKO-
dc.type.iprs특허-
dc.contributor.assignee한국과학기술연구원-
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KIST Patent > 2018
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