Full metadata record
DC Field | Value | Language |
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dc.contributor.author | Lu, W. | - |
dc.contributor.author | Roh, I. P. | - |
dc.contributor.author | Geum, D. -M. | - |
dc.contributor.author | del Alamo, J. A. | - |
dc.contributor.author | Song, J. D. | - |
dc.contributor.author | Kong, L. | - |
dc.contributor.author | Kim, S. -H. | - |
dc.date.accessioned | 2024-01-19T11:07:00Z | - |
dc.date.available | 2024-01-19T11:07:00Z | - |
dc.date.created | 2022-02-28 | - |
dc.date.issued | 2017-12 | - |
dc.identifier.issn | 2380-9248 | - |
dc.identifier.uri | https://pubs.kist.re.kr/handle/201004/114603 | - |
dc.description.abstract | We have fabricated self-aligned InGaSb p-channel FinFETs using a novel antimonide-compatible digital etch. This is the first demonstration of digital etch on InGaSb-based transistors of any kind. It has enabled the first fabricated InGaSb FinFETs featuring fin widths down to 10 nm and gate lengths of 20 nm. Single fin transistors with W-f = 10 nm and channel height of 23 nm (fin aspect ratio of 2.3) have achieved a record transconductance of 160 mu S/mu m at V-DS = 0.5 V. When normalized to device footprint, it reaches a record high g(m)= 704 mu S/mu m. Digital etch has been shown to effectively improve the turn-off characteristics of the devices. | - |
dc.language | English | - |
dc.publisher | IEEE | - |
dc.title | 10-nm Fin-Width InGaSb p-Channel Self-Aligned FinFETs Using Antimonide-Compatible Digital Etch | - |
dc.type | Conference | - |
dc.description.journalClass | 1 | - |
dc.identifier.bibliographicCitation | 63rd IEEE Annual International Electron Devices Meeting (IEDM) | - |
dc.citation.title | 63rd IEEE Annual International Electron Devices Meeting (IEDM) | - |
dc.citation.conferencePlace | US | - |
dc.citation.conferencePlace | San Francisco, CA | - |
dc.citation.conferenceDate | 2017-12-02 | - |
dc.relation.isPartOf | 2017 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM) | - |
dc.identifier.wosid | 000424868900106 | - |
dc.identifier.scopusid | 2-s2.0-85045186035 | - |
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