Full metadata record
DC Field | Value | Language |
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dc.contributor.author | El Dirani, H. | - |
dc.contributor.author | Bawedin, M. | - |
dc.contributor.author | Lee, K. | - |
dc.contributor.author | Parihar, M. | - |
dc.contributor.author | Mescot, X. | - |
dc.contributor.author | Fonteneau, P. | - |
dc.contributor.author | Galy, Ph. | - |
dc.contributor.author | Gamiz, F. | - |
dc.contributor.author | Kim, Y-T. | - |
dc.contributor.author | Ferrari, P. | - |
dc.contributor.author | Cristoloveanu, S. | - |
dc.date.accessioned | 2024-01-19T11:38:01Z | - |
dc.date.available | 2024-01-19T11:38:01Z | - |
dc.date.created | 2022-03-07 | - |
dc.date.issued | 2016-10 | - |
dc.identifier.uri | https://pubs.kist.re.kr/handle/201004/114973 | - |
dc.description.abstract | We demonstrate experimentally a capacitorless 1T-DRAM fabricated with 28 nm FDSOI. The Z(2)-FET memory cell features a large current sense margin and long retention time at T = 25 degrees C and 85 degrees C. Systematic measurements show that Z(2)-FET exhibits negligible OFF-state current at low drain/gate bias and is suitable as a low-power embedded memory. | - |
dc.language | English | - |
dc.publisher | IEEE | - |
dc.title | Competitive 1T-DRAM in 28 nm FDSOI Technology for Low-Power Embedded Memory | - |
dc.type | Conference | - |
dc.description.journalClass | 1 | - |
dc.identifier.bibliographicCitation | IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) | - |
dc.citation.title | IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) | - |
dc.citation.conferencePlace | US | - |
dc.citation.conferencePlace | Burlingame, CA | - |
dc.citation.conferenceDate | 2016-10-10 | - |
dc.relation.isPartOf | 2016 IEEE SOI-3D-SUBTHRESHOLD MICROELECTRONICS TECHNOLOGY UNIFIED CONFERENCE (S3S) | - |
dc.identifier.wosid | 000392693000033 | - |
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