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dc.contributor.authorCristoloveanu, S.-
dc.contributor.authorLee, K. H.-
dc.contributor.authorParihar, M. S.-
dc.contributor.authorEl Dirani, H.-
dc.contributor.authorLacord, J.-
dc.contributor.authorMartinie, S.-
dc.contributor.authorLe Royer, C.-
dc.contributor.authorBarbe, J. -Ch.-
dc.contributor.authorMescot, X.-
dc.contributor.authorFonteneau, P.-
dc.contributor.authorGaly, Ph.-
dc.contributor.authorGamiz, F.-
dc.contributor.authorNavarro, C.-
dc.contributor.authorCheng, B.-
dc.contributor.authorDuan, M.-
dc.contributor.authorAdamu-Lema, F.-
dc.contributor.authorAsenov, A.-
dc.contributor.authorTaur, Y.-
dc.contributor.authorXu, Y.-
dc.contributor.authorKim, Y-T.-
dc.contributor.authorWan, J.-
dc.contributor.authorBawedin, M.-
dc.date.accessioned2024-01-19T23:00:27Z-
dc.date.available2024-01-19T23:00:27Z-
dc.date.created2021-09-03-
dc.date.issued2018-05-
dc.identifier.issn0038-1101-
dc.identifier.urihttps://pubs.kist.re.kr/handle/201004/121409-
dc.description.abstractThe band-modulation and sharp-switching mechanisms in Z(2)-FET device operated as a capacitorless 1T-DRAM memory are reviewed. The main parameters that govern the memory performance are discussed based on detailed experiments and simulations. This 1T-DRAM memory does not suffer from super-coupling effect and can be integrated in sub-10 nm thick SOI films. It offers low leakage current, high current margin, long retention, low operating voltage especially for programming, and high speed. The Z(2)-FET is suitable for embedded memory applications.-
dc.languageEnglish-
dc.publisherPERGAMON-ELSEVIER SCIENCE LTD-
dc.subjectCAPACITORLESS 1T-DRAM-
dc.subjectBAND-MODULATION-
dc.subjectCELL-
dc.subjectTECHNOLOGY-
dc.subjectDEVICE-
dc.subjectNODE-
dc.subjectDRAM-
dc.titleA review of the Z(2)-FET 1T-DRAM memory: Operation mechanisms and key parameters-
dc.typeArticle-
dc.identifier.doi10.1016/j.sse.2017.11.012-
dc.description.journalClass1-
dc.identifier.bibliographicCitationSOLID-STATE ELECTRONICS, v.143, pp.10 - 19-
dc.citation.titleSOLID-STATE ELECTRONICS-
dc.citation.volume143-
dc.citation.startPage10-
dc.citation.endPage19-
dc.description.journalRegisteredClassscie-
dc.description.journalRegisteredClassscopus-
dc.identifier.wosid000430550600003-
dc.identifier.scopusid2-s2.0-85044381669-
dc.relation.journalWebOfScienceCategoryEngineering, Electrical & Electronic-
dc.relation.journalWebOfScienceCategoryPhysics, Applied-
dc.relation.journalWebOfScienceCategoryPhysics, Condensed Matter-
dc.relation.journalResearchAreaEngineering-
dc.relation.journalResearchAreaPhysics-
dc.type.docTypeArticle; Proceedings Paper-
dc.subject.keywordPlusCAPACITORLESS 1T-DRAM-
dc.subject.keywordPlusBAND-MODULATION-
dc.subject.keywordPlusCELL-
dc.subject.keywordPlusTECHNOLOGY-
dc.subject.keywordPlusDEVICE-
dc.subject.keywordPlusNODE-
dc.subject.keywordPlusDRAM-
dc.subject.keywordAuthor1T DRAM-
dc.subject.keywordAuthorZero subthreshold slope-
dc.subject.keywordAuthorZ2FET-
dc.subject.keywordAuthor10nm SOI film-
dc.subject.keywordAuthorLow power-
dc.subject.keywordAuthorhigh current margin-
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