Full metadata record
DC Field | Value | Language |
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dc.contributor.author | Kim, Seong Kwang | - |
dc.contributor.author | Lee, Jungmin | - |
dc.contributor.author | Geum, Dae-Myeong | - |
dc.contributor.author | Park, Min-Su | - |
dc.contributor.author | Choi, Won Jun | - |
dc.contributor.author | Choi, Sung-Jin | - |
dc.contributor.author | Kim, Dae Hwan | - |
dc.contributor.author | Kim, Sanghyeon | - |
dc.contributor.author | Kim, Dong Myong | - |
dc.date.accessioned | 2024-01-20T03:34:27Z | - |
dc.date.available | 2024-01-20T03:34:27Z | - |
dc.date.created | 2021-09-04 | - |
dc.date.issued | 2016-08 | - |
dc.identifier.issn | 0038-1101 | - |
dc.identifier.uri | https://pubs.kist.re.kr/handle/201004/123840 | - |
dc.description.abstract | We report characterization of the interface trap distribution (D-it(E)) over the bandgap in III-V metal-oxide- semiconductor field-effect transistors (MOSFETs) on insulator. Based only on the experimental subthreshold current data and differential coupling factor, we simultaneously obtained D-it(E) and a nonlinear mapping of the gate bias (V-GS) to the trap level (E-t) via the effective surface potential (psi(S),(eff)). The proposed technique allows direct extraction of the interface traps at the In0.53Ga0.47As-on insulator (-OI) MOSFETs only from the experimental subthreshold current data. Applying the technique to the In0.53Ga0.47As channel III-V-OI MOSFETs with the gate width/length W/L = 100/50, 100/25, and 100/10 mu m/mu m, we obtained D-it(E) congruent to 10(11)-10(12) eV(-1) cm(-2) over the bandgap without the dimension dependence. (C) 2016 Elsevier Ltd. All rights reserved. | - |
dc.language | English | - |
dc.publisher | PERGAMON-ELSEVIER SCIENCE LTD | - |
dc.subject | OXIDE INTERFACE | - |
dc.subject | STATES | - |
dc.title | Fully subthreshold current-based characterization of interface traps and surface potential in III-V-on-insulator MOSFETs | - |
dc.type | Article | - |
dc.identifier.doi | 10.1016/j.sse.2016.04.011 | - |
dc.description.journalClass | 1 | - |
dc.identifier.bibliographicCitation | SOLID-STATE ELECTRONICS, v.122, pp.8 - 12 | - |
dc.citation.title | SOLID-STATE ELECTRONICS | - |
dc.citation.volume | 122 | - |
dc.citation.startPage | 8 | - |
dc.citation.endPage | 12 | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.identifier.wosid | 000376199800002 | - |
dc.identifier.scopusid | 2-s2.0-84966304370 | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.relation.journalWebOfScienceCategory | Physics, Applied | - |
dc.relation.journalWebOfScienceCategory | Physics, Condensed Matter | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalResearchArea | Physics | - |
dc.type.docType | Article | - |
dc.subject.keywordPlus | OXIDE INTERFACE | - |
dc.subject.keywordPlus | STATES | - |
dc.subject.keywordAuthor | Interface trap | - |
dc.subject.keywordAuthor | InGaAs-OI MOSFETs | - |
dc.subject.keywordAuthor | III-V | - |
dc.subject.keywordAuthor | Subthreshold current model | - |
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