Fabrication of Pt/Sr2Bi2Ta2O9/Y2O3/Si FET and sub-circuit model for full memory chip design

Abstract

A metal-ferroelectric-insulator-semiconductor field-effect transistor (MFISFET) was fabricated with an inductively coupled plasma reactive-ion-etching (ICP-BIE) system without degradation of the ferroelectric characteristics. Y2O3 film and Sr2Bi2Ta2O9 (SBT) were used for the buffer insulating layer and the ferroelectric gate material, respectively. A dry etching process using ICP-RIE was carried out for removing the useless electrode and ferroelectric film, except for the gate regions. The fabricated MFISFET showed that the Y2O3 buffer insulating layer improved the characteristics of the ferroelectric memory. A counter-clockwise ID-VG hysteresis loop with 1.8-V threshold-voltage difference was presented, and the drain-current difference between the programmed on state and erased off state was more than four orders of magnitude. For the design and verification of the full memory chip, a sub-circuit model which is compatible with the conventional circuit simulator was proposed. The writing and reading operation of the proposed model was evaluated with an integrated-circuit emphasis (SPICE) simulator.