Operation of single transistor type ferroelectric random access memory

Authors
Shim, SIKim, SKim, YTPark, JH
Issue Date
2004-10-28
Publisher
INST ENGINEERING TECHNOLOGY-IET
Citation
ELECTRONICS LETTERS, v.40, no.22, pp.1397 - 1398
Abstract
Verification was sought for the memory operation of a single transistor type ferroelectric random access memory (IT type FeRAM) with a circuit model for a memory cell transistor combined with a precharged capacitive decoupling sensing scheme. The wiring scheme of the IT type FeRAM array was also proposed based on the operation of the fabricated memory cell transistor. As a result, the memory operation of IT type FeRAM was confirmed at a low current level with high sensing speed and no reference cell, and the design and verification of the full chip were achieved.
Keywords
CAPACITORS; CAPACITORS
ISSN
0013-5194
URI
https://pubs.kist.re.kr/handle/201004/137125
DOI
10.1049/el:20046555
Appears in Collections:
KIST Article > 2004
Files in This Item:
There are no files associated with this item.
Export
RIS (EndNote)
XLS (Excel)
XML

qrcode

Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.

BROWSE