Double-gate structure enabling remote Coulomb scattering-free transport in atomic-layer-deposited IGO thin-film transistors with HfO2 gate dielectric through insertion of SiO2 interlayer
- Authors
- Choi, Cheol Hee; Kim, Taikyu; Kim, Min Jae; Kim, Gwang-Bok; Oh, Jeong Eun; Jeong, Jae Kyeong
- Issue Date
- 2024-04
- Publisher
- Nature Publishing Group
- Citation
- Scientific Reports, v.14, no.1
- Abstract
- In this paper, high-performance indium gallium oxide (IGO) thin-film transistor (TFT) with a double-gate (DG) structure was developed using an atomic layer deposition route. The device consisting of 10-nm-thick IGO channel and 2/48-nm-thick SiO2/HfO2 dielectric was designed to be suitable for a display backplane in augmented and virtual reality applications. The fabricated DG TFTs exhibit outstanding device performances with field-effect mobility (mu(FE)) of 65.1 +/- 2.3 cm(2)V(-1) s(-1), subthreshold swing of 65 +/- 1 mVdec(-1), and threshold voltage (V-TH) of 0.42 +/- 0.05 V. Both the (mu(FE)) and SS are considerably improved by more than two-fold in the DG IGO TFTs compared to single-gate (SG) IGO TFTs. Important finding was that the DG mode of IGO TFTs exhibits the nearly temperature independent mu(FE) variations in contrast to the SG mode which suffers from the severe remote Coulomb scattering. The rationale for this disparity is discussed in detail based on the potential distribution along the vertical direction using technology computer-aided design simulation. Furthermore, the DG IGO TFTs exhibit a greatly improved reliability with negligible V-TH shift of - 0.22 V under a harsh negative bias thermal and illumination stress condition with an electric field of - 2 MVcm(-1) and blue light illumination at 80 degrees C for 3600 s. It could be attributed to the increased electrostatic potential that results in fast re-trapping of the electrons generated by the light-induced ionization of deep level oxygen vacancy defects.
- Keywords
- LOW-VOLTAGE; INGAZNO TRANSISTORS; OXIDE; MOBILITY; PERFORMANCE; CHANNEL; TEMPERATURE; INTERFACE; INSULATOR; HAFNIUM
- URI
- https://pubs.kist.re.kr/handle/201004/149685
- DOI
- 10.1038/s41598-024-58330-1
- Appears in Collections:
- KIST Article > 2024
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