Vertical Stacking of Atomic-Layer-Deposited Oxide Layers via a Fluorinated Graphene Transfer Technique
- Authors
- Kim, Hyunjun; Ryu, Huije; Jeong, Hyun Woo; Kim, Jiwoo; Moon, Donghoon; Mun, Sahngik Aaron; Hwang, Cheol Seong; Park, Min Hyuk; Son, Jang yup; Lee, Gwan-Hyoung
- Issue Date
- 2025-06
- Publisher
- American Chemical Society
- Citation
- ACS Nano, v.19, no.25, pp.23186 - 23192
- Abstract
- Monolithic three-dimensional (M3D) integration of semiconductor devices offers a distinct advantage over two-dimensional size scaling by achieving higher connection densities between the device layers. Still, it presents several technological challenges, including the fabrication of upper layers, where lattice mismatch complicates the deposition of high-quality oxide layers directly onto prefabricated devices. Additionally, high-temperature postprocesses can lead to intermixing and degradation of underlying layers. Here, we demonstrate a fluorinated graphene (FG) transfer technique that enables the integration of atomic-layer-deposited oxide semiconductors and dielectrics, overcoming lattice mismatch and minimizing intermixing. The dipole interaction between fluorine and carbon in FG enables the deposition of ultraflat and high-quality oxide thin films via atomic layer deposition (ALD). Upon heating to 400 degrees C, the dissociation of fluorine atoms from graphene (Gr) facilitates detachment and transfer of the oxide films. Using the FG transfer method, we fabricated multiple stacks of oxide thin films with clean van der Waals interfaces, effectively preventing intermixing during the postannealing process. Furthermore, we fabricated top-gate field-effect transistors (FETs) with MoS2 and ZnO channels by stacking Al2O3 as gate dielectric film, achieving high device performance thanks to a high-quality interface. We also demonstrate the transfer of patterned ALD-grown oxide thin films on a large scale using selective deposition and detachment of oxide thin films on the patterned FG. Our findings suggest that the FG transfer technique is a promising approach for advancing M3D integration and addressing challenges related to thermal budget constraints in semiconductor fabrication.
- Keywords
- INTEGRATION; THICKNESS; atomiclayer deposition; oxide films; transfer technique; fluorinated graphene; M3D integration; van der Waals interface
- ISSN
- 1936-0851
- URI
- https://pubs.kist.re.kr/handle/201004/152657
- DOI
- 10.1021/acsnano.5c04669
- Appears in Collections:
- KIST Article > Others
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