Physical Implementation of Reinforcement Learning via a Signal Summation Process in a Dual-Input Synaptic Transistor: Photoinduced Dipole Inversion of Au(I) Complex with Charge Traps of cPVP

Abstract

The rapid advancement of artificial intelligence (AI) has driven research beyond software into hardware innovation. To improve computational efficiency, AI accelerators integrating large numbers of transistors have been developed, yet this approach remains constrained by scaling and thermal limitations of silicon technology. Synaptic transistors, specialized for analog and parallel computation, have emerged as promising alternatives. Nevertheless, simply replacing silicon transistors offers limited improvement in reducing overall computational complexity. Here, we present a dual-input synaptic transistor that utilizes both light and voltage to enhance device-level computational efficiency through material functionality. The linear two-coordinate Au(I) complex, Au(DippPZI)(DPA), undergoes a ligand-to-ligand charge-transfer-induced dipole reversal upon photoexcitation, enabling photoinduced synaptic weight modulation. Complementarity, voltage-driven modulation arises from abundant ─OH trap sites in the cPVP layer. When light and voltage signals are applied simultaneously, these materials cooperatively generate an analog summation of synaptic current within a single device. The demonstrated transistor performs weight summation in reinforcement learning algorithms without requiring complex peripheral computation units, thereby reducing computational cost. This approach provides a versatile platform applicable to various learning algorithms that rely on summation operations, offering a new strategy for efficient hardware-level AI computation.