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dc.contributor.authorEun sung Park-
dc.contributor.authorHa, Won-Yong-
dc.contributor.authorEom, Do Yoon-
dc.contributor.authorAhn, Daehwan-
dc.contributor.authorAn, Hyuk-
dc.contributor.authorYi, Suhyun-
dc.contributor.authorKim, Kyung-Do-
dc.contributor.authorKim, Jongchae-
dc.contributor.authorChoi, Woo-Young-
dc.contributor.authorLee, Myung-Jae-
dc.date.accessioned2024-01-12T02:45:49Z-
dc.date.available2024-01-12T02:45:49Z-
dc.date.created2023-10-23-
dc.date.issued2023-06-15-
dc.identifier.urihttps://pubs.kist.re.kr/handle/201004/76419-
dc.identifier.urihttps://ieeexplore.ieee.org/document/10185229-
dc.description.abstractWe report on back-illuminated single-photon avalanche diodes (SPADs) based on 40 nm CIS technology. The SPAD performance is optimized with doping engineering, enabling the extension of the effective active area resulting in much higher efficiency. It achieves a dark count rate (DCR) of 15 cps/ μ m2, timing jitter of 97 ps, and excellent photon detection probability (PDP) in near-infrared (NIR) wavelength of about 60% at 905 nm and 44% at 940 nm at the excess bias voltage (VE) of 2.5 V.-
dc.languageEnglish-
dc.publisherInstitute of Electrical and Electronics Engineers Inc.-
dc.titleDoping-Optimized Back-illuminated Single-Photon Avalanche Diode in Stacked 40 nm CIS Technology Achieving 60% PDP at 905 nm-
dc.typeConference-
dc.identifier.doi10.23919/VLSITechnologyandCir57934.2023.10185229-
dc.description.journalClass1-
dc.identifier.bibliographicCitation2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023-
dc.citation.title2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023-
dc.citation.conferencePlaceJA-
dc.citation.conferencePlaceKyoto, Japan-
dc.citation.conferenceDate2023-06-11-
dc.relation.isPartOfDigest of Technical Papers - Symposium on VLSI Technology-
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KIST Conference Paper > 2023
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