CMOS 3D-Stacked FSI Multi-Channel Digital SiPM for Time-of-Flight PET Applications

Abstract

We present a frontside-illuminated (FSI) multichannel digital silicon photomultiplier (MD-SiPM) fabricated in 0.18 μm/0.18 μm 3D-stacked CMOS technology. The top tier is dedicated to the FSI photodetectors, while the bottom tier comprises timestamping, processing, and communication electronics. The MD-SiPM is segmented in two arrays of 8×8 clusters of 64 single-photon avalanche diode (SPAD) pixels each. A dedicated time-to-digital converter (TDC) is included within each cluster. The pixel pitch is 50 μm, the fill factor 67%, and the peak PDE 35% at 500 nm. The TDC is triggered by the first firing SPAD, and its identification code or address is propagated and stored by a winner-take-all architecture. The 128+1 TDCs, which are based on a multi-path gated ring oscillator, exhibit an LSB of 8 ps and a single-shot resolution of 50 ps (RMS) as determined through initial measurements on an independent structure. The power consumption per TDC is below 1.8 mW. The data is validated and read out from the clusters through an on-chip scheduling controller, while a random-access architecture enables access of each cluster individually. Preliminary characterization demonstrates the suitability of the system for the target application.