A Gradient-Gated SPAD Array for Non-Line-of-Sight Imaging
- Authors
- Zhao, Jiuxuan; Gramuglia, Francesco; Keshavarzian, Pouyan; Toh, Eng-Huat; Tng, Michelle; Lim, Louis; Dhulla, Vinit; Quek, Elgin; Lee, Myung-Jae; Charbon, Edoardo
- Issue Date
- 2024-01
- Publisher
- Institute of Electrical and Electronics Engineers
- Citation
- IEEE Journal on Selected Topics in Quantum Electronics, v.30, no.1, pp.1 - 10
- Abstract
- Time-resolved non-line-of-sight (NLOS) imaging based on single-photon avalanche diode (SPAD) detectors have demonstrated impressive results in recent years. To acquire adequate number of indirect photons from a hidden scene in the presence of overwhelming amount of early-arrival photons, a single-gated SPAD is widely employed to mitigate pile-up. However, additional prior knowledge of the hidden range and relay surface profile are required to preset the gating position and implement the reconstruction. With this work, we propose a gradient-gated technique to alleviate these shortcomings (pile-up and prior knowledge) in NLOS imaging with the development of a 6 × 6 SPAD array fabricated in a standard 55-nm Bipolar-CMOS-DMOS (BCD) technology. The SPAD sensor includes a delay-locked loop (DLL) block, a gating generator and a pixel array, which can be flexibly configured to free-running, single-gating and gradient-gating modes. The rise time of the gates is less than 450 ps (from 10% to 90%). In gradient-gating mode, the interval time between adjacent gates can be configured from 300 ps to 2 ns. In single-gating mode, the minimum gate window is measured below 5 ns. We demonstrated the sensor in a confocal NLOS imaging system that reconstructs hidden scenes with both retroreflective and diffuse objects. The presented scheme enables the development of calibration-free NLOS imaging modality for practical applications.
- Keywords
- RANGE; TDC; TIME; Imaging; Photonics; Nonlinear optics; Field programmable gate arrays; Detectors; BCD; CMOS; DLL; gating; gradient-gated; LiDAR; non-line-of-sight imaging; NLOS; pile-up; single-photon avalanche diode; SPAD; Single-photon avalanche diodes; Logic gates
- ISSN
- 1077-260X
- URI
- https://pubs.kist.re.kr/handle/201004/79900
- DOI
- 10.1109/jstqe.2023.3283150
- Appears in Collections:
- KIST Article > 2023
- Files in This Item:
There are no files associated with this item.
- Export
- RIS (EndNote)
- XLS (Excel)
- XML
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.