A Back-Illuminated SPAD Fabricated With 40 nm CMOS Image Sensor Technology Achieving Near 40% PDP at 940 nm

Abstract

This article introduces a back-illuminated (BI) single-photon avalanche diode (SPAD) based on 40 nm CMOS image sensor (CIS) technology which is the most advanced technology node for the fabrication of a SPAD up to date. It's based on a P-well (PW) and deep N-well (DNW) junction, and the DNW is deeply implanted to form a wide absorption region resulting in very high and wide photon detection probability (PDP). Thanks to the retrograde DNW, the premature edge breakdown phenomenon is completely prevented and the whole area of the planar junction becomes a high-efficient avalanche multiplication region. In addition, an anti-reflection coating on the backside of the SPAD and a metal reflector at the bottom reduce the reflection of incoming photons and improve the efficiency at long wavelengths, respectively. With the most advanced CIS technology for BI SPADs, the presented SPAD accomplishes a dark count rate (DCR) of 70 cps/μm 2 , peak PDP of 81% at 675 nm, and PDP of 39% at 940 nm. The timing jitter is 79 ps full width at half-maximum width (FWHM), which is the best timing jitter performance among BI SPADs reported so far. All the values are obtained with the excess bias voltage of 6 V.