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A pipelined architecture for VLSI implementation of quantizer/inverse quantizer processor for video CODEC.

Authors

KIM Hyoung Gon; Kwon Yong-Moo; 민남기; 김재형

Citation

Proceedings of the fifth international conference on signal processing applications & technology (IC, pp.1737 - 1742

URI

https://pubs.kist.re.kr/handle/201004/112120

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KIST Conference Paper > Others

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