Effect of Single Spinel Phase Crystallization on Drain-Induced-Barrier-Lowering in Submicron Length IZTO Thin-Film Transistors

Authors
Kim, Gwang-BokKim, TaikyuChoi, Cheol HeeChung, Sang WonJeong, Jae Kyeong
Issue Date
2023-07
Publisher
Institute of Electrical and Electronics Engineers
Citation
IEEE Electron Device Letters, v.44, no.7, pp.1132 - 1135
Abstract
This study shows the effect of single spinel phase crystallization on drain-induced barrier lowering (DIBL) of indium-zinc-tin-oxide (IZTO) thin-film transistors (TFTs) with submicron channel length. The 0.9-mu m-long amorphous IZTO (a-IZTO) TFT shows a poor DIBL of 318 mV/V. In contrast, a significant improvement in the DIBL is achieved in the single spinel phase IZTO (s-IZTO) TFT, which could be attributed to the suppression of lateral diffusion of oxygen vacancy (VO) and low VO defects through crystallization-induced enforcement of metal-oxygen bonds. Consequently, 0.9-mu m-long s-IZTO TFT reveals a small DIBL of 92 mV/V as well as a high field-effect mobility of 90.1 cm(2)/Vs and a low subthreshold swing of 0.1 V/dec. In addition, reliability against external bias temperature stress is considerably improved through single-phase crystallization, leading to an insignificant threshold voltage shift of +0.4 (-0.4) V under positive (negative) bias stress with electric field of 2 (-2) MV/cm at 60 degrees C for 10,000 s, respectively, in the 0.9-mu m-long s-IZTO TFT.
Keywords
CHANNEL; Oxide semiconductor; crystallization; drain induced barrier lowering; thin-film transistor
ISSN
0741-3106
URI
https://pubs.kist.re.kr/handle/201004/113489
DOI
10.1109/LED.2023.3274670
Appears in Collections:
KIST Article > 2023
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