Impact of Channel Length on the Operation of Junctionless Transistors With Substrate Biasing

Abstract

Junctionless transistors (JLTs) have promising advantages such as structural simplicity without p-n-junctions and bulk conduction-based operation for the realization of advanced complementary metal oxide semiconductor (CMOS) technologies. Here the channel-length dependence on the operation of JLTs with substrate biasing (V-gb) was investigated in detail. Parasitic series resistance (R-sd) noticeably decreased as V-gb increased. In addition, transconductance (g(m)), its derivative (dg(m)/dV(gf)), and ON-drain current (I-ON) in a short-channel JLT were significantly affected by the V-gb-modulated R-sd with charge coupling effects. This work provides important information for better understanding and true estimation of intrinsic JLT performance, for practical applications based on polycrystalline Si, III-V semiconductors, and transition metal dichalcogenides (TMDs) nano-materials as well as advanced logic devices.