On the Low-Frequency Noise Characterization of Z(2)-FET Devices

Authors
Marquez, CarlosNavarro, CarlosNavarro, SantiagoPadilla, Jose L.Donetti, LucaSampedro, CarlosGaly, PhilippeKim, Yong-TaeGamiz, Francisco
Issue Date
2019-02
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Citation
IEEE ACCESS, v.7, pp.42551 - 42556
Abstract
This paper addresses the low-frequency noise characterization of Z(2)-FET structures. These double-gated p-i-n diode devices have been fabricated at STMicroelectronics in an ultrathin body and box (UTBB) 28-nm FDSOI technology and designed to operate as 1T-DRAM memory cells, although other applications, as for example electro static discharge (ESD) protection, have been reported. The experimentally extracted power spectral density of current reveals that the high-diode series resistance, carrier number fluctuations due to oxide traps, and gate leakage current are the main noise contributors at high-current regimes. These mechanisms are expected to contribute to the degradation of cell variability and retention time. Higher flicker noise levels have been reported when increasing the vertical electric field. A simple model considering the contribution of the main noise sources is proposed.
Keywords
MECHANISMS; OPERATION; MECHANISMS; OPERATION; 1T-DRAM; noise measurement; p-i-n diodes; semiconductor device reliability; silicon on insulator technology; Z(2)-FET
ISSN
2169-3536
URI
https://pubs.kist.re.kr/handle/201004/120391
DOI
10.1109/ACCESS.2019.2907062
Appears in Collections:
KIST Article > 2019
Files in This Item:
There are no files associated with this item.
Export
RIS (EndNote)
XLS (Excel)
XML

qrcode

Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.

BROWSE