Extended Analysis of the Z(2)-FET: Operation as Capacitorless eDRAM

Abstract

The Z(2)-FET operation as capacitorless DRAM is analyzed using advanced 2-D TCAD simulations for IoT applications. The simulated architecture is built based on actual 28-nm fully depleted silicon-on-insulator devices. It is found that the triggering mechanism is dominated by the front-gate bias and the carrier's diffusion length. As in other FB-DRAMs, the memory window is defined by the ON voltage shift with the stored body charge. However, the Z(2)-FET's memory state is not exclusively defined by the inner charge but also by the reading conditions.