Microstructure Evolution and Defect Formation in Cu Through-Silicon Vias (TSVs) During Thermal Annealing

Abstract

The microstructural evolution of Cu through-silicon vias (TSVs) during thermal annealing was investigated by analyzing the Cu microstructure and the effects of twin boundaries and stress in the TSV. The Cu TSV had two regions with different grain sizes between the center and the edge with a random Cu texture before and after annealing. The grain size of large grains was almost unchanged after annealing, and the abrupt grain growth was restricted by the twin boundaries due to their structural stability. However, microvoids and cracks in the Cu TSV were observed after annealing. These defects were formed by the stress concentration among Cu grains. After defects were formed, the stress level of the TSV was decreased after annealing.