Low-frequency noise in high-k gate dielectric nanoscale MOSFETs

Abstract

The results of a simulation study on low-frequency excess noise in high-k SiO2/HfO2 dual dielectric n-MOSFETs are reported. Based on the 'Unified Model' where tunneling to traps in oxides is the major noise generation mechanism, we show how the low-frequency noise density and the frequency power index depend on the thickness of the interfacial oxide layer. Also, a simple and useful parameter extraction method for low-frequency noise is introduced.