The leakage current suppression mechanism in a RuO2/SrTiO3/Ru capacitor induced by introduction of an ultra-thin GeO2 interfacial layer at the bottom interface

Abstract

This study examines the chemical and electrical properties of RuO2/SrTiO3 (STO)/Ru and RuO2/STO/GeO2/Ru capacitors to elucidate the effect that a 6 & Aring;-thick GeO2 interfacial layer has on current leakage. The insertion of GeO2 at the STO/Ru interface effectively suppresses microstructural defect formation during STO deposition and post deposition annealing, which is a principal contributor to high leakage current. The Schottky barrier height increases from 0.32 eV (STO) to 0.74 eV (STO/GeO2), and the internal bias is alleviated from 0.9 V to 0.3 V, attributable to the improved STO/Ru contact properties obtained through preservation of the RuO2-x interfacial layer and by facilitating oxygen vacancy curing. Consequently, the STO/GeO2 material achieves a minimum equivalent oxide thickness of 0.40 nm at a physical thickness of 11 nm, which is a significant improvement over STO (0.69 nm at 27 nm). The conduction mechanisms under applied bias and the measured temperature of STO and STO/GeO2 were systematically analyzed, demonstrating that GeO2 interfacial engineering markedly improves dielectric performance in dynamic random access memory capacitors.