DSpace at KISTKIST Conference Paper2019

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dc.contributor.authorDae-Young Jeon-
dc.contributor.authorSo Jeong Park-
dc.contributor.authorMireille Mouis-
dc.contributor.authorSylvain Barraud-
dc.contributor.authorGyu-Tae Kim-
dc.contributor.authorGerard Ghibaudo-
dc.date.accessioned2024-01-12T05:40:51Z-
dc.date.available2024-01-12T05:40:51Z-
dc.date.created2021-09-29-
dc.date.issued2019-04-
dc.identifier.issn2330-5738-
dc.identifier.urihttps://pubs.kist.re.kr/handle/201004/78966-
dc.description.abstractUnique electrical properties of junctionless transistors (JLTs) with back-gate bias (Vgb) effects are investigated and visualized by numerical simulations. Charge coupling effects between front and back interfaces influenced threshold voltage (Vth) and flat-band voltage (Vfb) of JLTs. In addition, series resistance (Rsd) of JLTs was dependent on Vgb and back-biasing behavior of JLT with a shorter channel was deviated from intrinsic characteristics due to considerable Rsd effects. The Rsd was extracted by transfer length method (TLM) and its effects were deembedded using simple equation.-
dc.languageEnglish-
dc.publisherIEEE-
dc.subjectSeries resistance-
dc.subjectnull-
dc.subjectBack-gate effects-
dc.subjectnull-
dc.subjectJunctionless transistors-
dc.subjectnull-
dc.subjectThreshold voltage-
dc.subjectnull-
dc.subjectFlat-band voltage-
dc.titleSeries Resistance Effects on the Back-gate Biased Operation of Junctionless Transistors-
dc.typeConference-
dc.description.journalClass1-
dc.identifier.bibliographicCitationEUROSOI-ULIS2019-
dc.citation.titleEUROSOI-ULIS2019-
dc.citation.conferencePlaceFR-
dc.citation.conferencePlaceGrenoble, France-
dc.citation.conferenceDate2019-04-01-
dc.relation.isPartOf2019 JOINT INTERNATIONAL EUROSOI WORKSHOP AND INTERNATIONAL CONFERENCE ON ULTIMATE INTEGRATION ON SILICON (EUROSOI-ULIS)-
dc.identifier.wosid000565067300067-
dc.identifier.scopusid2-s2.0-85083160657-
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