Controlling the Effective Channel Thickness of Junctionless Transistors by Substrate Bias

Abstract

Substrate-bias-affected unique electrical characteristics of junctionless transistors (JLTs) were investigated in detail. Bulk channel thickness of JLTs (t(si_ eff)) was effectively modulated by back-gate bias (V-gb). The variation in threshold voltage (V-th) and mobility degradation were observed in the reduced t(si_eff), due to the negative V-gb-induced depletion of free electrons. The V-gb effect was also influenced significantly by the doping concentration in JLTs. In addition, numerical simulations verified those results and analytical equations explained well the experimental results.