A Simple Method for Estimation of Silicon Film Thickness in T-Gate Junction less Transistors

Authors
Jeon, Dae-YoungPark, So JeongMouis, MireilleBarraud, SylvainKim, Gyu-TaeGhibaudo, Gerard
Issue Date
2018-09
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Citation
IEEE ELECTRON DEVICE LETTERS, v.39, no.9, pp.1282 - 1285
Abstract
Junction less transistors (JLTs) without PN-junctions near the source/drain are promising candidates for further development of CMOS technology. The Si thickness of tri-gate JLTs is crucial to understand their unique electrical properties related to bulk neutral and surface accumulation conduction. A simple method based on a unique operation mechanism is suggested for extraction of t(si) from measurements on tri-gate JLTs. The method was successfully applied to fabricated tri-gate JLTs and the extracted t(si) values were comparable with those of transmission electron microscopy. Furthermore, the validity of the method was confirmed by 2-D numerical simulation.
Keywords
NANOWIRE TRANSISTORS; CHANNEL WIDTH; NANOWIRE TRANSISTORS; CHANNEL WIDTH; Junctionless transistors (JLTs); Si thickness (t(si)); bulk neutral channel; surface accumulation channel; method for parameter extraction; numerical simulation
ISSN
0741-3106
URI
https://pubs.kist.re.kr/handle/201004/120982
DOI
10.1109/LED.2018.2857623
Appears in Collections:
KIST Article > 2018
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