A review of the Z(2)-FET 1T-DRAM memory: Operation mechanisms and key parameters
- Authors
- Cristoloveanu, S.; Lee, K. H.; Parihar, M. S.; El Dirani, H.; Lacord, J.; Martinie, S.; Le Royer, C.; Barbe, J. -Ch.; Mescot, X.; Fonteneau, P.; Galy, Ph.; Gamiz, F.; Navarro, C.; Cheng, B.; Duan, M.; Adamu-Lema, F.; Asenov, A.; Taur, Y.; Xu, Y.; Kim, Y-T.; Wan, J.; Bawedin, M.
- Issue Date
- 2018-05
- Publisher
- PERGAMON-ELSEVIER SCIENCE LTD
- Citation
- SOLID-STATE ELECTRONICS, v.143, pp.10 - 19
- Abstract
- The band-modulation and sharp-switching mechanisms in Z(2)-FET device operated as a capacitorless 1T-DRAM memory are reviewed. The main parameters that govern the memory performance are discussed based on detailed experiments and simulations. This 1T-DRAM memory does not suffer from super-coupling effect and can be integrated in sub-10 nm thick SOI films. It offers low leakage current, high current margin, long retention, low operating voltage especially for programming, and high speed. The Z(2)-FET is suitable for embedded memory applications.
- Keywords
- CAPACITORLESS 1T-DRAM; BAND-MODULATION; CELL; TECHNOLOGY; DEVICE; NODE; DRAM; CAPACITORLESS 1T-DRAM; BAND-MODULATION; CELL; TECHNOLOGY; DEVICE; NODE; DRAM; 1T DRAM; Zero subthreshold slope; Z2FET; 10nm SOI film; Low power; high current margin
- ISSN
- 0038-1101
- URI
- https://pubs.kist.re.kr/handle/201004/121409
- DOI
- 10.1016/j.sse.2017.11.012
- Appears in Collections:
- KIST Article > 2018
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