Fabrication of InGaAs-on-Insulator Substrates Using Direct Wafer-Bonding and Epitaxial Lift-Off Techniques

Authors
Kim, Seong KwangShim, Jae-PhilGeum, Dae-MyeongKim, Chang ZooKim, Han-SungSong, Jin DongChoi, Sung-JinKim, Dae HwanChoi, Won JunKim, Hyung-JunKim, Dong MyongKim, Sanghyeon
Issue Date
2017-09
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Citation
IEEE TRANSACTIONS ON ELECTRON DEVICES, v.64, no.9, pp.3594 - 3601
Abstract
Defect less semiconductor-on-insulator (-OI) by a cost-effective and low-temperature process is strongly needed for monolithic 3-D integration. Toward this, in this paper, we present a cost-effective fabrication of the indium gallium arsenide-OI structure featuring the direct wafer bonding (DWB) and epitaxial lift-off (ELO) techniques as well as the reuse of the indium phosphide donor wafer. We systematically investigated the effects of the prepatterning of the III-V layer before DWB and surface reforming (hydrophilic) to speed up the ELO process for a fast and high-throughput process, which is essential for cost reduction. Thismethod provides an excellent crystal quality of In0.53Ga0.47As on Si. Crystal quality of the film was evaluated using Raman spectra, and transmission electron microscope. Finally, we achieved good electrical properties of In0.53Ga0.47As-OImetal-oxide-semiconductorfield-effect-transistors fabricated through the proposed DWB and ELO.
Keywords
III-V; III-V compound semiconductor; epitaxial lift-off (ELO); indium gallium arsenide (InGaAs); InGaAs-on-insulator (OI); metal-oxide-semiconductor field-effect-transistors (MOSFETs); wafer bonding
ISSN
0018-9383
URI
https://pubs.kist.re.kr/handle/201004/122344
DOI
10.1109/TED.2017.2722482
Appears in Collections:
KIST Article > 2017
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